Fractional-N frequency synthesizers can be used to overcome many limitations associated with integer-N frequency synthesizers. In fractional-N frequency synthesizers, the effective frequency divide ratio is a fractional number, which enables a relatively high frequency reference signal to be used to achieve fine resolution of frequencies in synthesizer output signals. This fractional number is typically achieved by periodically changing an integer divide ratio so that a desired fractional number can be approximated. One typical disadvantage associated with fractional-N frequency synthesis is the generation of unwanted low-frequency “spurs” by a dual-modulus (or multi-modulus) divider. These spurs make fractional-N frequency synthesizers impractical for many applications unless they are suppressed to a negligible level. Conventional spur reduction techniques include: (i) digital-to-analog (DAC) phase estimation, (ii) random jittering, which randomizes a divide ratio, (iii) sigma-delta (ΣΔ) noise shaping, which modulates a divide ratio, (iv) phase interpolation; and (v) pulse generation. Some of these spur reduction techniques are disclosed in articles by: S. Pamarti et al., entitled “A Spur Elimination Technique for Phase Interpolation-Based Fractional-N PLLs”, IEEE Trans. on Circuits and Systems, Vol. 55, No. 6, pp. 1639-1647, July (2008); and Li Zhang et al., entitled “A Hybrid Spur Compensation Technique for Finite-Modulo Fractional-N Phase-Locked Loops”, IEEE Journal of Solid-State Circuits, Vol. 44, No. 11, pp. 2922-2934, November (2009).
As illustrated by FIG. 1A, a frequency synthesizer 10 may include a fractional-N divider 12 within a feedback path of a phase-locked loop (PLL), which filters jitter in the output of the divider 12. This fractional-N divider 12 may operate by modulating between two or more integer values. The phase-locked loop of FIG. 1A contains a phase detector 14, which receives an input reference signal (e.g., 25 MHz), a charge pump 16, a loop filter 18 and a voltage-controlled oscillator (VCO) 20. This VCO 20 generates an output signal having a frequency that is a non-integer multiple of the frequency of the input reference signal. An integer divider 22 may also be provided for generating an output signal at a reduced frequency relative to the VCO output signal. Examples of the frequency synthesizer 10 of FIG. 1A are disclosed at U.S. Pat. No. 7,532,081 to Partridge et al., entitled “Frequency and/or Phase Compensated Microelectromechanical Oscillator,” and FIG. 3 of U.S. Pat. No. 7,417,510 to Huang, entitled “Direct Digital Interpolative Synthesis”. 
FIG. 1B illustrates a frequency synthesizer 10′, which includes an integer divider 12′ within a feedback path of a phase-locked loop (PLL). This phase-locked loop contains a phase detector 14, which receives an input reference signal (e.g., 25 MHz), a charge pump 16, a loop filter 18 and a voltage-controlled oscillator (VCO) 20, which generates an output signal having a frequency that is an integer multiple of the frequency of the input reference signal. Multiple fractional-N dividers 22a-22d may be provided for generating output signals having different frequencies, which do not have integer relationships with the output frequency of the VCO 20. As will be understood by those skilled in the art, additional circuitry may be needed to reduce jitter in the signals generated by the dividers 22a-22d. The dividers 22a-22d may be provided as interpolative dividers as disclosed at FIGS. 4-6 of the '510 patent to Huang. For example, as shown by FIG. 5 of Huang, an interpolative divider can include a fractional-N divider, which receives a VCO clock. A first order delta sigma modulator receives a digital divide ratio (M/N). The integer portion of the digital divide ratio is supplied to the fractional-N divider as a divide control signal, which can be a stream of integers that approximate the fractional divide ratio. A digital quantization error, which corresponds to the fractional portion of the divide ratio, is supplied to a digitally controlled phase interpolator. The jitter introduced by the fractional-N divider can be canceled by interpolation in the phase interpolator, which is based on the digital quantization error supplied by the delta sigma modulator. In this manner, the input clock from the VCO is first divided down by the fractional-N divider according to the control information provided by the delta sigma modulator and then the phase interpolator operates to cancel quantization errors in the output of the fractional-N divider. Additional examples of fractional-N frequency synthesizers, which utilize an accumulator within a numerically-controlled oscillator and a phase interpolator, are disclosed at FIG. 6 of the '510 patent to Huang and in U.S. Pat. No. 7,724,097 to Carley et al., entitled “Direct Digital Synthesizer for Reference Frequency Generation.” Moreover, a fractional-N divider having divider modulation circuits therein with segmented accumulators is disclosed in commonly assigned U.S. application Ser. No. 13/425,761, filed Mar. 21, 2012, the disclosure of which is hereby incorporated herein by reference.
An additional frequency synthesizer that may utilize frequency margining techniques to generate a finely controllable clock is disclosed in U.S. Pat. No. 7,800,451 to Fu et al., entitled “Frequency Adjustment for Clock Generator.” In addition, a low phase-noise frequency synthesizer with a frequency margining capability that supports output frequency variations of ±5% from nominal is disclosed in a publicly available datasheet from the assignee of the present application, entitled “FemtoClocks Crystal-to-LVPECL 350 MHz Frequency Margining Synthesizer,” ICS843207-350 (2007).